Description
Senior DFT Engineer needed with extensive experience in the deployment and implementation of industry standard DFT techniques as pertaining to large complex ASIC's that include;
Full scan insertion of designs having multiple clock domains, debugging and diagnosing scan rule violations
Automation test pattern generation (ATPG) and test coverage improvement methods
Memory BIST and Boundary scan logic (Jtag)
test pattern verification in various test modes
Analyzing reports from DFT and STA tools
Prefer at least 8 years or more of direct, hands-on experience in full chip DFT
Tool Experience required: DFT Compiler, BSD Compiler, Tetramax, Logic Vision, VCS, Primetime. Strong working knowledge of Perl, tcl, make, Linux/Unix shell script.!
Apply Here
Salary: 137500 - 162500

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